Mode of access: World Wide Web.

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Part of: Synthesis digital library of engineering and computer science.

Includes bibliographical references (pages 61-81).

1. Introduction -- 1.1 From the beginning -- 1.2 The end of Dennard scaling and the switch to multicores -- 1.3 Dark silicon, the utilization wall, and the rise of the heterogeneous parallelism -- 1.4 Other issues and future directions -- 1.5 About the book -- 1.5.1 Differences from the prior synthesis lecture [103] -- 1.5.2 Target audience --

2. Voltage and frequency management -- 2.1 Technology background and trends -- 2.1.1 Relation of V and f -- 2.1.2 Technology solutions -- 2.1.3 DVFS latency -- 2.1.4 DVFS granularity -- 2.2 Models of frequency vs. performance and power -- 2.2.1 Analytical models -- 2.2.2 Correlation-based power models -- 2.2.3 A combined power and performance model -- 2.3 OS-managed DVFS techniques -- 2.3.1 Discovering and exploiting deadlines -- 2.3.2 Linux DVFS governors -- 2.4 Parallelism and criticality -- 2.4.1 Thread- and task-level criticality: static scheduling -- 2.4.2 Thread- and task-level criticality: dynamic scheduling -- 2.4.3 Criticality -- 2.5 Chapter summary --

3. Heterogeneity and specialization -- 3.1 Dark silicon -- 3.1.1 Dark silicon analysis and models -- 3.1.2 Designing for dark silicon: brief examples -- 3.1.3 The sentiments against dark silicon -- 3.2 Heterogeneity in on-chip CPUs -- 3.2.1 Current industry approaches -- 3.2.2 Research and future trends -- 3.3 Single-ISA configurable heterogeneity -- 3.4 Mixing GPUs and CPUs -- 3.4.1 CPU-GPU pairs: the power-performance rationale -- 3.4.2 Industry examples -- 3.4.3 Selected research examples -- 3.5 Accelerators -- 3.5.1 Background -- 3.5.2 Selected research -- 3.5.3 Industry examples -- 3.6 Reliability vs. energy tradeoffs -- 3.7 Chapter summary --

4. Communication and memory systems -- 4.1 The energy cost of data motion: a holistic view -- 4.2 Power awareness in on-chip interconnect: techniques and trends -- 4.2.1 Background and industry state -- 4.2.2 Power efficiency of interconnect links -- 4.2.3 Exploiting emerging technologies to improve power efficiency -- 4.3 Power awareness in data storage: caches and scratchpads -- 4.3.1 Cache hierarchies and power efficiency -- 4.3.2 Cache associativity and its implication on power -- 4.3.3 Cache resizing and static power -- 4.3.4 Cache coherence -- 4.3.5 The power implications of scratchpad memories -- 4.4 Chapter summary --

5. Conclusions -- 5.1 Future trends: technology challenges and drivers -- 5.2 Future trends: emerging applications and domains -- 5.3 Final summary -- Bibliography -- Authors' biographies.

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

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As Moore's Law and Dennard scaling trends have slowed, the challenges of building high-performance computer architectures while maintaining acceptable power efficiency levels have heightened. Over the past ten years, architecture techniques for power efficiency have shifted from primarily focusing on module-level efficiencies, toward more holistic design styles based on parallelism and heterogeneity. This work highlights and synthesizes recent techniques and trends in power-efficient computer architecture.

Also available in print.

Title from PDF title page (viewed on January 17, 2015).